1. Field of the Invention
The present invention relates to a semiconductor device having an electrode pad and manufacturing method thereof.
2. Description of the Related Art
In semiconductor device, an electrode pad for ensuring the electrical connection to the external may be formed on the top layer interconnect of the interconnect structure patterned on semiconductor substrate. An example of a method for manufacturing a semiconductor device having the electrode pad will be described as follows.
FIGS. 10A to 10D and FIGS. 11A and 11B are cross sectional views showing process steps for manufacturing a conventional semiconductor device. FIGS. 10A to 10D and FIGS. 11A and 11B are schematic diagrams for the use in illustrating the processes, and thickness of each layer shown in the figures such as a multilayer film 111 are different from the actual dimension ratio.
First, the multilayer film 111 having a laminated structure of interconnect layers, interlayer insulating films and so on are formed on a silicon substrate 110, as shown in FIG. 10A. A Cu interconnect 112 is formed on the interlayer insulating film disposed as the top layer thereof. Subsequently, an interlayer insulating film 114 having a dual layer structure including SiON and SiO2 is formed, and via holes 122 opening from the Cu interconnect 112 is formed (FIG. 10A).
Subsequently, a TiN film 115, a pad metal film 117 and a TiN film 121 are formed in turn on the interlayer insulating film 114, and thereafter, these layers are patterned to a dimension suitable for mounting of the solder ball, and thus the pad electrode is formed (FIG. 10B).
Subsequently, a polyimide film 118 is formed so as to cover the pad metal film 117, and thereafter, the polyimide film 118 is patterned to provide an aperture 119, and thus the pad metal film 117 is partially exposed (FIG. 10C). Thereafter, the TiN film 121 on the bottom of the aperture 119 is removed by wet etch processing to obtain the pad electrode structure shown in FIG. 10D.
As an approach for improving the reliability of thus obtainable pad electrode, the following approaches have conventionally been used.
In JP-A-2001-15,516, a technology of reducing the stress occurred in the bonding process to prevent the deterioration of copper interconnect by forming an Al pad at a position of a passivation insulation film slightly slid from the copper pad position, and by inhibiting the transfer of oxygen into the copper interconnect, is proposed. This configuration corresponds to forming the pad metal film 117 to the position where it is slightly slid from the right overhead of the Cu interconnect 112, by association with FIGS. 10A to 10D.
In addition, in JP-A-2000-91,341, a technology for forming an inert alloy of CuTix layer on the surface of the copper bond pad to inhibit the formation of intermetallic compounds thereon, and thus providing the direct bonding of the aluminum or the gold interconnect onto the copper bond pad. This will be described corresponding to the configuration of FIGS. 10A to 10D: a configuration comprising a silicon substrate 110, multi-layer films 111, a Cu interconnect 112 and an interlayer insulating film 114, where a CuTix layer is formed on the surface of the Cu interconnect 112, is provided. In the process described in JP-A-2000-91,341, the un-reacted Ti layer is removed to expose CuTix layer over the surface of the Cu interconnect 112.
Here, when an inspection of the electrical properties of the semiconductor device formed on a semiconductor wafer is carried out, a manner of conducting the inspection by contacting the waveguide probe onto the electrode pad of the device to be inspected may be adopted. That is, in the process of an actual non-defective/defective screening, the inspections of the properties are conducted by a manner where the pad metal film 117 is poked with a probe under a condition shown in FIG. 10D. In this occasion, since the conventional semiconductor device does not have enough impact resistance, the pad metal film 117 and the TiN film 115 underlying thereof may be peeled off when the surface of the pad electrode is poked with a probe, thereby exposing the Cu interconnect 112.
In the semiconductor device of JP-A-2001-15,516, although a certain level of strength is maintained since the Ti film and the TiN film are formed on the upper surface of the copper interconnect, the upper layer of the copper interconnect is damaged when it is poked with the probe for the non-defective/defective screening, thereby the copper interconnect is exposed.
In this way, when Cu interconnect 112 exposes with the condition of FIG. 10D, the surface of the Cu interconnect 112 that is exposed to oxygen in the atmosphere and water is oxidized and corroded. That is, a film of copper oxide 123 is formed on the surface of the Cu interconnect 112 (FIG. 11A). This may deteriorate the interconnect structure. Thus, it is difficult to inhibit the corrosion of the copper interconnect of the case of being poked with the probe, by only moving the installation position of the Al pad from a right overhead of the interconnect layer.
In addition, the semiconductor device of the JP-A-2000-91,341 has an effect of preventing the corrosion of Cu in a certain level, since the device has the CuTix layer on the surface of the copper bond pad. However, since the device does not have enough mechanical strength against the impact, the surface of copper bond pad is damaged when it is poked with the probe in the non-defective/defective screening, and copper is eventually exposed.
Thus, the technology of having only a step of forming the CuTix layer on the upper part of the copper bond pad may cause a problem, in which the copper bond pad is damaged when it is poked with the probe and similarly the corrosion occurs therein.
Thus, the conventional semiconductor device does not have enough impact resistance against the impact from the direction of the top surface of the substrate in the process of the non-defective/defective screening. In addition, it is required to have a semiconductor device, which can inhibit causing the corrosion of the exposed surface when the copper interconnect is exposed by the impacts.